The invention relates generally to the field of semiconductor devices and, more particularly, to RAM-logic tiles for use in field programmable gate arrays.
A gate array, a type of integrated circuit device, is a large two-dimensional matrix of logic blocks, each of which is typically equivalent to one or a few logic gates. These logic blocks are overlaid with one or more interconnection layers, which connect the logic blocks in a pattern to perform a user-specified function.
A type of gate array, the field programmable gate array (FPGA), is formed with a global set of vertical and horizontal wiring lines and a local set of wiring segments built into the device. The wiring segments are electrically isolated from the logic blocks and each other by electrically programmable interconnect elements. One such element is an antifuse. The user programs these antifuses to define the specified interconnection pattern for the user's application, very rapidly and at the user's own facility.
However, traditional FPGAs have had the problem that their operation may be relatively slow as compared to other types of gate arrays. One solution to this problem is the FPGA disclosed in U.S. Pat. No. 5,313,119, issued May 17, 1994 to L. H. Cooke et al., and assigned to the present assignee. The specification of which is hereby incorporated by reference for all purposes.
The present invention provides an integrated circuit RAM-logic tile (RLT) that is designed to efficiently implement both memory structures and sequential logic elements. The RLTs of the present invention provide substantial speed advantages over RLTs heretofore known. An embodiment of the RLT according to the present invention is a drop-in replacement for the latch-logic blocks of the FPGA disclosed in U.S. Pat. No. 5,313,119, previously incorporated by reference.